The present application relates to semiconductor technology. More particularly, the present application relates to semiconductor structures containing FinFET anti-fuses with reduced breakdown voltage which can be readily integrated with high performance FinFETs. The present application also relates to methods of forming such semiconductor structures.
An anti-fuse is an electrical device that performs the opposite function to a fuse. Whereas a fuse starts with a low resistance and is designed to permanently break an electrically conductive path (typically when the current through the path exceeds a specified limit), an anti-fuse starts with a high resistance and is designed to permanently create an electrically conductive path (typically when the voltage across the anti-fuse exceeds a certain level).
Programmable on-chip anti-fuses are needed in many circuit applications. In some applications, it preferable to fabricate on-chip anti-fuses during FinFET CMOS fabrication in order to minimize process cost and improve system integration. Using the same dielectric material as the gate dielectric and the anti-fuse dielectric will simplify process complexity. The breakdown voltage of conventional planar anti-fuses with a gate dielectric is too high. Also, planar anti-fuses use too much area compatible with current ground rules of 10 nm or 7 nm technology. Therefore, there is a need for improved on-chip FinFET compatible anti-fuses.